Broadway (microprocessor)

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IBM Broadway microprocessor from the inside of a Wii. The reference to Canada in the picture is related to where it was packaged i.e. by IBM Canada in Bromont.
ProducedFrom 2006 to Present[citation needed]
Designed byIBM and Nintendo
Common manufacturer(s)
Max. CPU clock rate729 MHz
Min. feature size90 nm (2006-2007), 65 nm (2007-present)
Instruction setPower Architecture (PowerPC ISA 1.10)
MicroarchitecturePowerPC G3
L1 cache32/32 kB
L2 cache256 kB

Template:Power Architecture

Broadway is the codename of the 32-bit Central Processing Unit (CPU) used in Nintendo's Wii video game console. It was designed by IBM, and is currently being produced using a 65 nm SOI process.

According to IBM, the processor consumes 20% less power than its predecessor, the 180 nm Gekko used in the Nintendo GameCube video game console.[1]

Broadway is being produced by IBM at their 300 mm semiconductor development and manufacturing facility in East Fishkill, New York. The bond, assembly, and test operation for the Broadway module is performed at the IBM facility in Bromont, Quebec. Very few official details have been released to the public by Nintendo or IBM. Unofficial reports claim it is derived from the 486 MHz Gekko architecture used in the GameCube and runs 50% faster at 729 MHz.[2]

The PowerPC 750CL, released in 2006, is a stock CPU offered by IBM and virtually identical to Broadway. The only difference is that the 750CL comes in variants, ranging from 400 MHz up to 1000 MHz.[3][4][5]

Specifications[edit | edit source]

  • 90 nanometer process technology, shrunk to 65 nm in 2007. [6]
  • Superscalar Out-of-order execution Power Architecture core, specially modified for the Wii platform
  • IBM silicon on insulator (SOI) technology
  • Backward compatible with the Gekko processor
  • 729 MHz
  • 4 stages long Two integer ALUs(IU1 and IU2) - 32 bit
  • 7 stages long 64-bit floating-point unit(FPU) (or 2 × 32-bit SIMD, often found under the denomination "paired singles")
  • Branch Prediction Unit(BPU)
  • Load-Store Unit(LSU)
  • System Register Unit(SRU)
  • Memory Management Unit (MMU)
  • Branch Target Instruction Cache(BTIC)
  • SIMD Instructions - PowerPC750 + Roughly 50 new SIMD instructions, geared toward 3D graphics
  • 64 kB L1 cache (32 kB instruction + 32 kB data)
  • 256 kB L2 cache
  • 2.9 GFLOPS

External bus[edit | edit source]

  • 64-bit
  • 243 MHz
  • 1.944 gigabytes per second bandwidth

Gallery[edit | edit source]

39X6735, 2006
90 nm, 21×21 mm package 
Broadway A
43E4048, 2006-2007
90 nm, 21×21 mm package 
Broadway B
43E5070, 2007-2008
65 nm, 21×21 mm package 
48J2662, 2008-present
65 nm, 15×15 mm package 
These images are illustrations and only approximately to scale.

References[edit | edit source]